Faculty Development

Capacity-building workshops for educators to enhance academic programs in semiconductors

Develop Faculty Leadership in Semiconductor Assembly, Test and Packaging

Faculty from higher education institutions in ITSI Partner Countries are invited to join a collaborative program to enhance semiconductor education. Gain the expertise to develop industry-ready professionals and strengthen your institution’s academic offerings.

Semiconductor Faculty Certification (SFC) Program

This program supports faculty in planning and implementing semiconductor assembly, test and packaging (ATP) programs. Participants will engage in an ATP-focused learning experience, earning two Microcredential Badges, each with 4 micro-badges from Arizona State University. After completing the ATP learning experience, two 5-day development workshops (Faculty Development and ASU Design Clinics) will be offered in country to provide hands-on support from ASU faculty and industry experts to develop and enhance semiconductor curriculum plans to support the development of industry-ready professionals and strengthen your institution’s academic offerings .

Participant Benefits and Outcomes

  • Grant-paid learning to complete (2) ATP-focused microcredential badges from ASU Engineering
  • ASU faculty consultation to inform team curriculum proposal
  • Learning design support on team curriculum plan
  • Semiconductor Faculty Certification from ASU
  • A vetted curriculum plan to guide implementation of semiconductor ATP program(s) at home university

Faculty Participant Criteria

To participate in the SFC Program, faculty must meet the following criteria:
  • Faculty must be nominated by university leadership.
  • Groups must consist of 5-6 faculty members from each identified university.
  • Faculty must be from the disciplines of Electrical, Materials, Mechanical, or Industrial engineering.
  • Faculty members must have a minimum of a Master’s degree, with a PhD preferred.
  • Faculty must demonstrate English language proficiency at Level B2 or higher.
Semiconductor Faculty Certification (SFC) Program
open to faculty from higher education institutions who are committed to planning, developing, and implementing semiconductor assembly, test and packaging (ATP) programs.

Faculty Development from Higher Education Institutions

ITSI Program Path

Click on each step to review

1. Apply

Eligible faculty from ITSI partner countries will request a nomination letter from their institution and complete the application form. Institutions must all provide a letter of commitment. Below is the timeline for the application process

  • Partner Institutions will provide a letter of commitment to faculty by 8/07/24
  • Nominated faculty must complete the application form by 8/14/2024 including the nomination form received from their institution.
  • Faculty will be notified of the decision by 8/19/2024.

2. Acceptance

5–6 individuals from each institution will be selected to participate in the SFC program. Once selected, faculty will need to participate in a virtual orientation session that will serve as the official launch of the program. This virtual orientation is scheduled for 8/28/2024.

3. Learn

Faculty will engage in a structured learning experience, starting with two 40-hour Microcredential Badges focused on semiconductor ATP. These courses will be conducted live on Zoom, providing interactive and in-depth instruction on key topics such as packaging fundamentals, electrical concepts, and testing. Below is the schedule for each badge.

Semiconductor Packaging Foundational Concepts and Drivers

September 3-26, 2024 | Monday, Tuesday, and Thursday| 5:30–9 p.m. MST

  • Intro to Semiconductor Packaging & Design
  • Intro to Electrical Concepts in Semiconductor Packaging
  • Intro to Thermal Management & Mechanical Properties of Packages
  • Intro to Packaging Materials, Manufacturing, Test, and Reliability

Semiconductor Packaging, Assembly, and Test

October 7–31, 2024 | Monday, Tuesday, and Thursday | 5:30–9 p.m. MST

  • 2D Packaging & Assembly
  • Materials Selection for Thermo-Mechanical & Electrical Performance
  • Application of Electrical & Thermo-Mechanical Modelling
  • Test & Data Analysis for Quality & Reliability

ASU Stackable microcredentials are created and taught by faculty and industry experts. The two microcredential badges taught in this program were created and will be instructed by:

 

4. Design

Following the learning phase, faculty will participate in two 5-day workshops aimed at developing and finalizing their curriculum plans. 

Faculty Development Workshop - 5 days in-person | In-country

The first workshop, the Faculty Development Workshop, will be held in-country and will focus on exploring curriculum choices, collaborating with industry representatives to define required skills, and deciding upon a curriculum enhancement to pursue. This workshop will involve interactive sessions, hands-on activities, and collaborative discussions. Mark your calendars for the following dates to participate in the Faculty Development Workshop. 

  • Costa Rica - 11/18/2024 - 11/22/2024
  • Vietnam - 12/09/2024- 12/13/2024
  • Philippines - 12/03/2024 - 12/13/2024

 

ASU Design Clinic - 5 days in-person | In-country | Dates TBA- Spring 2024

The second workshop, the ASU Curriculum Design Workshop, will also be held in-country and will bring together institutional faculty teams to develop and present a final curriculum plan. Participants will work closely with ASU instructional designers to refine their plans and instructional pedagogy. The workshop will culminate in presentations of their unique curriculum designs, ensuring they are well-prepared to implement these programs at their home institutions. Mark your calendars for the following dates to participate in the ASU Design Clinic. 

  • Costa Rica - 1/20/2025 - 1/24/2025
  • Vietnam - 2/03/2025- 2/07/2025
  • Philippines - 2/10/2025 - 2/14/2025

5. Implement

Upon completion of the program, faculty will work across their institution to introduce new semiconductor ATP courses and curricula, preparing students for successful careers in the semiconductor industry. This implementation phase will leverage the knowledge and skills gained through the program, ensuring that faculty are equipped to develop industry-ready professionals and strengthen their institution’s academic offerings.

Lead the expansion of semiconductor education at your university

Huyen Nguyen

Program Coordinator, Indo-Pacific Region

Huyen Nguyen is the Program Coordinator, Indo-Pacific Region for the Diversifying Semiconductor Supply Chain project in the Vietnam representative office for Ira A. Fulton Schools of Engineering at Arizona State University. Huyen supports the coordination and implementation of ISTI activities in the Indo-Pacific region countries.

Ha Mai

Data Analyst

Ha Mai serves as Data Analyst in the Vietnam representative office for Ira A. Fulton Schools of Engineering at Arizona State University (ASU) and the Diversifying Semiconductor Supply Chain project. Ha supports the collection and management of ITSI project datasets, ensuring data accuracy and integrity.

Melissa Stine

Program Manager, Americas Region

Melissa Stine is the Program Manager of Strategic Initiatives in the Ira A. Fulton Schools of Engineering at Arizona State University (ASU) and the Program Manager, Americas Region, for the Diversifying Semiconductor Supply Chain project, overseeing the implementation of project activities within the Americas Region countries.

Dung Le

Program Manager, Indo-Pacific Region

Dung Le serves as Program Manager, Indo-Pacific Region for the Diversifying Semiconductor Supply Chain project in the Vietnam representative office for Ira A. Fulton Schools of Engineering at Arizona State University (ASU), overseeing the implementation of project activities within the Indo-Pacific region countries.

Thai Tran

Sr. Manager for Monitoring and Evaluation

Thai Tran serves as Sr. Manager for Monitoring and Evaluation in the Vietnam representative office for Ira A. Fulton Schools of Engineering at Arizona State University (ASU) and the Diversifying Semiconductor Supply Chain project. Thai oversees the comprehensive quality assurance of all ITSI project deliverables, ensuring activities meet project KPIs and align with the established quality criteria.

Jesús Silva

Associate Director of Program Operations

Jesús Silva Elizalde serves as the Associate Director of Operations for the International Technology Security and Innovation (ITSI) Fund, Diversifying Semiconductor Supply Chains Project in the Ira A. Fulton Schools of Engineering at Arizona State University (ASU). Leveraging vast USAID, Chips Act, and semiconductor experience, Jesús oversees the implementation of all ITSI activities.

Jose Quiroga

Managing Director

Jose A. Quiroga is the Director of Global Development in the Ira A. Fulton Schools of Engineering (FSE) at Arizona State University (ASU) and the Managing Director of the Diversifying Semiconductor Supply Chains Project at ASU, funded by the US Department of State through the International Technology Security and Innovation (ITSI) Fund. This program aims to enhance workforce capabilities within semiconductor assembly, testing, and packaging (ATP) operations across key partner countries. By prioritizing workforce development activities, the initiative seeks to create a sustainable pipeline of skilled professionals essential for the semiconductor industry’s growth and resilience.

Jeffrey Goss

Principal Investigator

Jeffrey Goss is a prominent leader in global and professional development, holding roles as Associate Vice Provost SE Asia, Executive Director, and Assistant Dean in the Ira A. Fulton Schools of Engineering at Arizona State University (ASU). With over 25 years of experience, he has significantly impacted STEM education and workforce development globally. Mr. Goss is Principal Investigator for the International Technology Security and Innovation (ITSI) Fund. His leadership has advanced STEM education and strengthened supply chains in the Americas and Indo-Pacific, enhancing global semiconductor ecosystems.